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Universal Style Transfer using Deep Layer Aggregation

This project is the base code for the authentication microservice fo the IDP project.

Optimizarea unui algoritm de Machine Learning

Public repository for ASC.

A board-level simulator with GUI for FPGA boards, based on Xilinx Vivado Simulator.

Programming framework/library for MRA (Map-Reduce Accelerator)

Container setup for emulating Ethernet and CAN traffic