65085c1a by Mark Charlebois Committed by Behan Webster

percpu

See http://kernel.opensuse.org/cgit/kernel/commit/?id=509eb76ebf97

The use of sp as a register variable is not supported in clang and
the behavior they are working around in GCC may not even be present
in clang.

From the link above:

Unfortunately, GCC doesn't treat a "memory" clobber on a non-volatile
asm block as a side-effect, and will happily re-order it before other
memory clobbers (including those in prempt_disable()) and cache the
value. This has been observed to break the cmpxchg logic in the slub
allocator, leading to livelock in kmem_cache_alloc in mainline kernels.

Because the GCC workaround causes numerous warnings, revert the change
until it can be verified that it is in fact an issue for clang.


Signed-off-by: Mark Charlebois <charlebm@gmail.com>
Signed-off-by: Behan Webster <behanw@converseincode.com>
1 parent bcfe8777
......@@ -11,5 +11,35 @@
*/
#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
#if defined(CONFIG_SMP) && !defined(CONFIG_CPU_V6)
/*
* Read TPIDRPRW.
* GCC requires a workaround as it does not treat a "memory" clobber on a
* non-volatile asm block as a side-effect.
* We want to allow caching the value, so for GCC avoid using volatile and
* instead use a fake stack read to hazard against barrier().
*/
#if defined(__clang__)
static inline unsigned long read_TPIDRPRW(void) {
unsigned long off;
/*
* Read TPIDRPRW.
*/
asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : : "memory");
return off;
}
#else
static inline unsigned long read_TPIDRPRW(void) {
unsigned long off;
register unsigned long *sp asm ("sp");
asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : "Q" (*sp));
return off;
}
#endif
#endif
#endif /* __ASM_ARM_COMPILER_H */
......
......@@ -27,21 +27,10 @@ static inline void set_my_cpu_offset(unsigned long off)
asm volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (off) : "memory");
}
static inline unsigned long __my_cpu_offset(void)
{
unsigned long off;
register unsigned long *sp asm ("sp");
#include "asm/compiler.h"
/*
* Read TPIDRPRW.
* We want to allow caching the value, so avoid using volatile and
* instead use a fake stack read to hazard against barrier().
*/
asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : "Q" (*sp));
#define __my_cpu_offset read_TPIDRPRW()
return off;
}
#define __my_cpu_offset __my_cpu_offset()
#else
#define set_my_cpu_offset(x) do {} while(0)
......